4510 is an edge-triggered synchronous up/down BCD counter. It can count up or down in BCD pattern depending upon the input states. It has four input and four output pins for the respective BCD input and output. The four parallel outputs carrying the BCD output are obtained at pins O0, O1, O2 & O3 with O3 being the most significant bit (MSB).
When the parallel load (pin1) is high, BCD data is loaded from the input to output pins. Otherwise it is kept at low. The up or down counting mode is selected by Up/Down pin. The counting occurs on a low to high transition at the clock input when the clock enable pin is set low.
The output at terminal count (pin7) goes low when a count of 1111/0000 is reached in up/down counting. A high signal on master reset pin, resets the counter irrespective of the inputs.
|1||Loads BCD from input to output pins||Parallel Load|
|2||Output pin 3||Output3|
|3||Input pin 3||Input3|
|4||Input pin 0||Input0|
|5||Clock enable input; Active low||Clock Enable|
|6||Output pin 0||Output 0|
|7||Terminal count output; Active low||Terminal Count|
|9||Resets the counter; Active high||Master Reset|
|10||Input pin for up/down select;High for up & low for down counting||Up/Down|
|11||Output pin 1||Output1|
|12||Input pin 1||Input1|
|13||Input pin 2||Input2|
|14||Output pin 2||Output2|
|15||Clock pulse input||Clock Input|
|16||Supply voltage; 5V (3V – 18V)||Vcc|