How to Communicate with PC using RS232 Protocol
1. Parallel communication: In this, more than one wire is connected between two communicating node. Each bit is sent separately on dedicated wire. In this approach, numbers of wires required=width of data bus. This is preferred for short way communication. Over a long distance, this increases cost of wires and maintenance.
2. Serial Communication: In this, data is combined into a packet and sent bit by bit on a single wire between two communicating devices. This requires less costly implementation and maintenance. However, synchronization between communicating devices is necessary. Sometimes separate wires are required for two-way communication. This approach is widely used for long distance, high speed and reliable communication.
Serial communication using UART (Universal Asynchronous Receiver/Transmitter) is widely used in embedded systems. Almost all controller has inbuilt UART available for easy communication. IBM PC also comes with serial COM PORTS so that we can communicate with them using controllers. Using USB to serial bridge, we can create virtual COM PORTS and communicate with controllers using the same.
Baud rate is the measurement of speed of data transfer for serial communications. Various baud rate supported by UART for given maximum distance is as follows.
Controllers are connected with device using DB9 connector. As the name suggests, it has 9 pins as shown in image. Function of pins required for serial communication are explained below.
1.CD/DCD (CARRIER DETECT/ DATA CARRIER DETECT)
2.RxD (Receiver Pin)
3.TxD (Transmission Pin)
4.DTR (Data Terminal Ready)
5.GND (Signal Ground)
6.DSR (Data Set Ready)
7.RTS (Request To Send)
8.CTS (Clear To Send)
9.RI (Ring Indicator)
Out of these 9 pins, only 3 (RxD, TxD and GND) pins are necessary for serial communication between PC and controller. Connection is as shown.
So we need a voltage converter which can convert one logic level to another. MAX232 IC with four capacitors does this task. MAX233 IC performs the same task without external capacitors connected. However, MAX232 is widely used because of low cost and availability. Connections with MAX232 IC are as shown below.
Important registers for UART0 with functions are listed here.
1. U0RBR- Receiver Buffer- Received data from UART0 is first stored in this register.
2. U0THR-Transmit Hold Register- Data to be transmitted on UART0 must be given to this register.
3. U0LCR- Line Control Register- It has bits to enable DLL (BIT 7), Set break (BIT 6), Stick Parity select (BIT 5), Even Parity select (BIT 4), Parity Enable (BIT 3), Number of stop bits (BIT 2) and Word length (BIT 1 and BIT 0)
4. U0LSR- Line Status Register- It reflects the status of UART0. 8 bits of this register from MSB to LSB are RX FIFO Error, TEMT, THRE,BI,FE,PE,OE and DR.
Baud rate for UART can be calculated by formula,
Where, PCLK= Peripheral Clock Frequency
U0DLM, U0DLL are standard UART0 baud rate generator divider registers
MULVAL and DIVADDVAL are fraction generator values. They must meet following conditions.
0<MULVAL, DIVADDVAL<=15 with MULVAL=0 treated as MULVAL=1.
Let us understand all registers individually.
There is a stack allocated for the received data storage. The U0RBR (UART0 RECEIVER BUFFER) is the top byte of the UART0 Rx FIFO. The top byte of the Rx FIFO contains the oldest character received via serial port which can be read from the bus. The LSB (bit 0) represents the “oldest” received data bit. If the character received is less than 8 bits, the unused MSBs are padded with zeroes.
The Divisor Latch Access Bit (DLAB) in U0LCR must be cleared in order to access the U0RBR. The U0RBR is always Read Only register used to store the received data.
Data to be sent over serial com has to be first kept in register UOTHR (UART0 transmit holding register). The U0THR is the top byte of the UART0 TX FIFO. The top byte is the newest character in the TX FIFO and can be written via the bus interface. The LSB represents the first bit to transmit.
The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the U0THR. The U0THR is always Write only register to temporary store data to be transmitted over serial com.
UOLCR (UART0 LINE CONTROL REGISTER) determines the format of the data to be transmitted over UART0. It is an 8 bit register. Function of each pin is as follows.
· Bit 0:1 for data length
o 00: 5 bits
o 01: 6 bits
o 10: 7 bits
o 11: 8 bits
· Bit 2 for stop bit length
o 0: 1 stop bit
o 1: 2 stop bits
· Bit 3 for parity configurations
o 0: Parity generation and checking is disabled
o 1: Parity generation and checking is enabled
· Bit 5:4 for parity select (required only if bit 3 is set to logic 1)
o 00: Odd parity. Number of 1s in the transmitted character and theattached parity bit will be odd
o 01: Even Parity. Number of 1s in the transmitted character and theattached parity bit will be even
o 10: Forced “1” stick parity
o 11: Forced “0” stick parity
· Bit 6 for Break control
o 0: Disable breaks transmission
o 1: Enable breaks transmission. Output pin UART0 TXD is forcedto logic 0 when U0LCR  is active high
· Bit 7 for DLAB (Divisor Latch Access Bit)
o 0: Disable access to Divisor Latch
o 1: Enableaccess to Divisor Latch
The U0LSR (UART0 LINE STATUS REGISTER) is a read-only register that provides status information on the UART0 TX andRX blocks.It is an 8 bit register. Function of each pin is as follows.
· Bit 0- Receiver Data Ready (RDR)
o U0LSR0 is set when the U0RBR holds an unread character and is clearedwhen the UART0 RBR FIFO is empty.
o 0:U0RBR is empty.
o 1: U0RBR contains valid data
· Bit 1- Overrun error (OE)
o The overrun error condition is set as soon as it occurs. An U0LSR read clearsU0LSR1. U0LSR1 is set when UART0 RSR has a new character assembledand the UART0 RBR FIFO is full. In this case, the UART0 RBR FIFO will notbe overwritten and the character in the UART0 RSR will be lost.
o 0: Overrun error status is inactive
o 1: Overrun error status is active
· Bit 2- Parity Error (PE)
o When the parity bit of a received character is in the wrong state, a parity erroroccurs. An U0LSR read clears U0LSR. Time of parity error detection isdependent on U0FCR.
o 0: Parity error status is inactive
o 1: Parity error status is active
· Bit 3- Framing Error (FE)
o When the stop bit of a received character is at logic 0, a framing error occurs.An U0LSR read clears U0LSR. The time of the framing error detection isdependent on U0FCR0. Upon detection of a framing error, the Rx will attemptto resynchronize to the data and assume that the bad stop bit is actually anearly start bit. However, it cannot be assumed that the next received byte willbe correct even if there is no Framing Error.
o 0: Framing error status is inactive.
o 1: Framing error status is active
· Bit 4- Break Interrupt (BI)
o When RXD0 is held in the spacing state (all 0’s) for one full charactertransmission (start, data, parity, stop), a break interrupt occurs. Once thebreak condition has been detected, the receiver goes idle until RXD0 goes tomarking state (all 1’s). An U0LSR read clears this status bit. The time of breakdetection is dependent on U0FCR.
o 0: Break interrupt status is inactive.
o 1: Break interrupt status is active.
· Bit 5- TransmitterHoldingRegister Empty (THRE)
o THRE is set immediately upon detection of an empty UART0 THR and iscleared on a U0THR write.
o 0: U0THR contains valid data
o 1: U0THR is empty
· Bit 6- TransmitterEmpty(TEMT)
o TEMT is set when both U0THR and U0TSR are empty; TEMT is cleared wheneither the U0TSR or the U0THR contain valid data.
o 0: U0THR and/or the U0TSR contain valid data.
o 1: U0THR and the U0TSR are empty.
· Bit 7- Error in RXFIFO(RXFE)
o U0LSR is set when a character with a Rx error such as framing error, parityerror or break interrupt, is loaded into the U0RBR. This bit is cleared when theU0LSR register is read and there are no subsequent errors in the UART0FIFO.
o 0: U0RBR contains no UART0 RX errors or U0FCR =0